Second Scarab Microarchitectural Simulator Workshop
(MICRO'26)

Overview

Microarchitectural simulation is a cornerstone of computer‑architecture research: it allows us to validate hypotheses, explore design alternatives, and project future performance. Credible studies demand (i) faithful models of modern out‑of‑order CPUs, (ii) representative workloads executed at scale, and (iii) productive workflows that combine fast runtime with automated management and analysis.

The Scarab simulator meets these goals. It provides a highly detailed yet configurable out‑of‑order CPU model featuring a decoupled frontend with instruction prefetchers, accurate branch predictors, and a micro‑op cache; realistic register renaming; multiple scheduling policies and diversified functional units; a comprehensively parameterized memory hierarchy with contemporary cache replacement and prefetching techniques; and cycle‑level DRAM timing via Ramulator. Scarab implements accurate wrong‑path execution and supports both execution‑driven (Pin‑based) and trace‑driven modes, while still delivering hundreds of thousands of simulated instructions per second.

Beyond the core simulator, Scarab‑infra offers an industry‑grade ecosystem: curated SimPoints and traces, a fully containerized environment, seamless Slurm integration, and analysis notebooks that implement the Top‑Down methodology—enabling large‑scale, reproducible studies.

This second edition builds on the first Scarab workshop held at MICRO 2025 in Seoul. Attendees new to Scarab will get a complete introduction, while returning participants will find updated material on the latest simulator and infrastructure features. No prior Scarab experience is required; bring a laptop for the hands‑on sessions.